The present invention relates to techniques for reducing the number of terminals requiring probes when probe testing and wafer level burn-in is performed in fabrication process steps for fabricating a semiconductor device.
In recent years, as the degree of shrinking and integration of semiconductor devices has been enhanced, development of system LSI has become mainstream. In a system LSI, integrated circuits having various different functions are placed within a single chip or a single package, and individual power supply systems and ground systems provided for the integrated circuits, respectively, have to be integrated as a single power supply system and a single ground system of the chip or of the package.
However, when influences of noise interference between a digital circuit and an analog circuit or between a plurality of analog circuits due to sharing of a power supply system and a ground system is not negligible, normally, using some kind of means, power supply systems and ground systems have to be separated. As a result, a plurality of power supply terminals and a plurality of ground terminals have to be provided. The number of required power supply terminals and ground terminals is increased as the degree of integration is increased.
In process steps for fabricating a semiconductor integrated circuit, as the degree of shrinking and integration has been enhanced, the number of chips obtained from a single wafer has been increased. Especially, since recent arrival of 300 mm wafer, this tendency has become more prominent. Therefore, in process steps of fabricating a semiconductor integrated circuit in mass production, how efficiently testing and burn-in can be performed at low cost has become a challenge.
One of the most effective solutions to this challenge is to examine a plurality of integrated circuits by a single test. Especially, in recent years, there are an increased number of cases where wafer level burn-in, i.e., burn-in to be performed at a wafer level, is applied even for packaged products and thus a stress can be applied to the integrated circuits in a lump for each wafer. In this testing technique, as the degree of integration is enhanced and the number of chips obtained from a single wafer is increased, its effects in efficiency and cost performance become larger. By the same token, in for probe testing, when the number of chips obtained from a single wafer is increased, an immense amount of time is required to test a single wafer, and therefore a plurality of semiconductor integrated circuits (e.g., 8, 16 or 32 semiconductor integrated circuits) are tested at the same time to increase efficiency and reduce costs for testing.
However, in this technique, the number of probes becomes a problem. Especially, in wafer level burn-in, since the number of probes provided per chip is limited because of restrictions for a burn-in equipment, it is not possible to apply probes to all pads of a system LSI at the same time. Needless to say, this problem more largely influences as the number of chips obtained from a single wafer is increased.
In addition, as has been described, in a system LSI, a plurality of different power supply systems exist and a large number of power supply terminals and ground terminals exist. Therefore, the number of pads requiring probes when wafer level burn-in is performed is likely to be increased and thus the number of probes becomes a more serious problem.
To solve this problem, according to a first known technique, respective power supply lines of a plurality of circuit blocks are connected to separate power supply pads, respectively, and a switch circuit is provided between a specific one of the power supply lines and each of the other ones of the power supply lines. When testing is performed, a power supply potential is applied to one of the power supply pads connected to the specific one of the power supply lines and the switch circuits are turned to be in a conduction state (see U.S. Pat. No. 5,404,099).
According to a second known technique, as a measure against ESD (electrostatic discharge), inter-power-supply protection transistors are provided so that each of the protection transistors is connected in parallel to each switch circuit between the power supply lines. As another option, each of the inter-power-supply protection transistors serves as a switch circuit between power supply lines (see United States Patent Application Publication No. 2005/0067899).
However, in each of the first and second known techniques, when wafer level burn-in is performed, a power supply potential is supplied to a plurality of circuit blocks via their respective switch circuits from a single power pad, so that a difference in potential level between power supply potentials of the plurality of circuit blocks is generated. The difference in potential level corresponds to an amount of a voltage drop due to an ON resistance of each switch circuit. Therefore, wafer level burn-in is performed in a state where respective potentials applied to the plurality of circuit blocks are different and a stress level becomes non-uniform in a semiconductor integrated circuit.